1. Field of the Invention
The present invention relates to circuit-pattern-data correction methods and semiconductor-device manufacturing methods, and particularly to a circuit-pattern-data correction method and a semiconductor-device manufacturing method which reduce the influence of a proximity effect, produced when a circuit pattern is formed on a wafer according to design data for a semiconductor device.
2. Description of the Related Art
As semiconductor devices have been using finer patterns due to higher integration these days, the influence of a proximity effect appears greatly in an exposure process, disabling semiconductor devices to be manufactured according to the design data. To prevent this from occurring, proximity effect correction (optical proximity correction, hereinafter called OPC) for correcting a circuit pattern in design data has been generally employed in recent years so that the influence of the proximity effect is understood beforehand to obtain dimensions as designed.
OPC includes rule-based OPC and model-based OPC. The rule-based OPC performs corrections based on a correction table which specifies the amount of correction according to the width of each circuit pattern and the distance to an adjacent circuit pattern in design data. On the other hand, the model-based OPC performs corrections with the use of optical-intensity simulation, and is suited to correct complicated-shape circuit patterns for which corrections are difficult with the rule-based OPC. It is said that the model-based OPC is almost required for fine machining in the generation of 65 nm or less.
FIGS. 17A and 17B are outline views used for explaining the model-based OPC.
It is assumed here that correction is made according to the model-based OPC with a circuit pattern 500a shown in FIG. 17A being used as a target figure. In the model-based OPC, a figure is divided into sides having certain lengths at division points 501 by using the vertexes of the figure. Then, an evaluation point 502 is specified on each side, and the evaluation point 502 is moved for correction with the use of simulation to have appropriate values, such as the width and space, after exposure. For example, a corrected circuit pattern 500b shown in FIG. 17B is generated to obtain an optical-intensity simulation image 503 which matches the target figure (circuit pattern 500a) indicated by a dotted line, at the evaluation points 502. This optical-intensity simulation image 503 indicates the actual shape of a photomask such as a reticle or a resist circuit pattern to be formed on a wafer.
Since the model-based OPC is based on optical-intensity simulation, it is difficult to correct factors, such as the influence of etching, caused by processes other than lithography.
Therefore, a method is used in which the original design data is corrected first with the use of the rule-based OPC and then the model-based OPC is applied to the corrected design data.
Techniques employing the rule-based OPC to reduce the amount of data and to prevent minute protrusions, digging, and steps (differences in level) from occurring in a circuit pattern during correction are disclosed, for example, in Japanese Unexamined Patent Application Publication Nos. 2002-072441 and 2002-083757.
If a step produced when the rule-based OPC is applied is located in a vicinity of a circuit pattern corner, overcorrection is made by the model-based OPC, which is the next step, to cause a broken line and other problems.
FIGS. 18A and 18B are outline views used for explaining a model-based OPC employed when minute steps are located in vicinities of circuit pattern corners.
It is assumed here that correction is made according to the model-based OPC with a circuit pattern 510a, shown in FIG. 18A, obtained when the rule-based OPC is applied, being used as a target figure. As described earlier, in the model-based OPC, division points 511 are specified by using the vertexes of the figure. Therefore, when a step is located in a vicinity of a circuit pattern corner, a division point 511 is specified in a vicinity of the circuit pattern corner. Then, an evaluation point 512 is also specified close to the circuit pattern corner.
At circuit pattern corners, as indicated by an optical-intensity simulation image 513 shown in FIG. 18B, a resist cannot be patterned in the same way as the target figure, and is rounded. Therefore, when an evaluation point 512 is located close to a circuit pattern corner, excessive correction is made as indicated by a corrected circuit pattern 510b so that the optical-intensity simulation image 513 is made close to the target figure at the evaluation point 512. Using such a corrected circuit pattern 510b causes a narrow part or a broken line not intended.